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Synchronous DRAM (60X Bus)
done with four MT48LC8M16A2 by Micron or compatibles, which are each 2M X 16bit X
4banks.
The SDRAM’s timing is controlled by SDRAM Machine #1 associated with 60X bus, via
its assigned chip select lines (See Figure 5-5). The SDRAM Machine supports PBI (Page
Bank Interleave) which increases the SDRAM throughput. The SDRAM connection
scheme is shown in Figure 5-5.
CS2
SDRAS
SDCAS
SDWE
BANKSEL(1:2)
A17
SDA10
A19
A(20:28)
SDDQM(0:7)
D(0:63)
SYSCLK
CS0
RAS
CAS
WE
BA(1:0)
A11
A10
A9
A(8:0)
DQMB(0:7)
DQ(0:63)
CKE
CLK
MT48LC8M16A2-6
Figure 5-5. 60x SDRAM Connection Scheme
5.6.1
SDRAM Programming
After power-up, the SDRAM needs to be initialized by means of programming to establish
its mode of operation. The SDRAM is programmed according to the following procedure:
1. Issue Precharge-All command.
2. Issue 8 CBR refresh commands.
3. Issue MODE-SET command.
An SDRAM is programmed by issuing a mode register set command. During that
command, data is passed to the mode register through the SDRAM’s address lines. This
command is fully supported by the SDRAM machine of the MPC8272. Before that can
occur, the SDRAM machine of the MPC8272 must be initialized.
MPC8272ADS User Guide
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